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Altera_Forum
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14 years ago

Bidirectional buffer

Hi, I am working on Altera FPGA. Please help me to code a Bidirectional bus using HDL. Can anyone share a code for this. Regards, freak
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Altera_Forum
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12 years ago

'X' means the signal has an undefined state. This is because when data_out_ena = '0', io_data is tristated and it's supposed to be driven by an external source. If you dont' specify any external signal, data_in state is indeed undefined.