bad configuration snheme of MSEL , cycloneIII

Hi Amzi,

you could be a little bit more precise in describing the problem. Start by telling what device you use and what you mean by the wording "configuration time". If this is the time until conf_done goes high then, depending on the amount of configuration data, this may be OK for fast mode.

Harald

It all depends on the size of your image.

The Data Clk is 40MHz so the transfer rate is 40Mbit/s

Altera say...

AS configuration time is dominated by the time it takes to transfer data from the EPCS to the FPGA device. The AS interface is clocked by the FPGA DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40 MHz oscillator is 20 MHz (50 ns). For example, the maximum AS configuration time estimate for EP3C10 device is (2.5 MBits of uncompressed data) = RBF Size x (maximum DCLK period / 1 bit per DCLK cycle) = 2.5 MBits x (50 ns / 1 bit) = 125 ms.

http://www.altera.com/support/devices/configuration/cfg-compare.html?gsa_pos=7&wt.oss_r=1&wt.oss=config%20time (http://www.altera.com/support/devices/configuration/cfg-compare.html?gsa_pos=7&wt.oss_r=1&wt.oss=config%20time)

So 240ms is not unreasonable

Hope this helps

Vern

thanks ,

I'm use the EP3C80 .

what about my first problem : I select MSEL scheme for a 2.5V/3.0V when in fact the MSEL signals are connected to 3.3V and the programming device is connecting to 3.3V too.

unimportant selection?