Honored Contributor
Honored ContributorIt all depends on the size of your image.
The Data Clk is 40MHz so the transfer rate is 40Mbit/s Altera say... AS configuration time is dominated by the time it takes to transfer data from the EPCS to the FPGA device. The AS interface is clocked by the FPGA DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40 MHz oscillator is 20 MHz (50 ns). For example, the maximum AS configuration time estimate for EP3C10 device is (2.5 MBits of uncompressed data) = RBF Size x (maximum DCLK period / 1 bit per DCLK cycle) = 2.5 MBits x (50 ns / 1 bit) = 125 ms. http://www.altera.com/support/devices/configuration/cfg-compare.html?gsa_pos=7&wt.oss_r=1&wt.oss=config%20time (http://www.altera.com/support/devices/configuration/cfg-compare.html?gsa_pos=7&wt.oss_r=1&wt.oss=config%20time) So 240ms is not unreasonable Hope this helps Vern
