backspace and enter key, reset VGA in verilog HDL?

There is one typical syntax mistake commonly done.

assign h_end = (h_count_reg == (HD+HF+HB+HR-1));

You use == what is a logical equality its result can be unknown, you should better use === what is case equality and will only result in true or false

assign h_end = (h_count_reg === (HD+HF+HB+HR-1));

Next thing. inside an always construct, you better use the non blocking assignment <= instead of the single =.

Your code shows only the the video synchronisation signals, but no video information itself. No RGB signal shown, i assume this must be done somewhere else where the video_on signal is use ...

`define MAXIMUM_H 80

`define MAXIMUM_V 30

//`define back_space 7'h7f

module text_pixel_generation_circuit(clk, reset, text_on, w_enable, ascii_in, pixel_x, pixel_y, text_rgb);

input clk, reset;

input text_on, w_enable;

input wire [6:0] ascii_in;

input wire [9:0] pixel_x;

input wire [9:0] pixel_y;

output reg [2:0] text_rgb;

// signal declaration

//character rom

wire [10:0] rom_address;

wire [6:0] char_address;

wire [3:0] row_address;

wire [2:0] bit_address;

wire [7:0] font_word;

wire font_bit;

// Synchronous Dual Port RAM Block declaration

reg [6:0] ram [0:4095]; // RAM text buffer

reg [11:0] write_addr; // RAM write address

reg [11:0] read_addr; // RAM read address

reg [4:0] write_row_address; // RAM write row

//wire [4:0] write_row_address_next;

reg [6:0] write_bit_address; // RAM write column

//wire [6:0] write_bit_address_next;

reg [6:0] read_data; // RAM read data

reg [6:0] write_data; // RAM write data

// tile RAM

//wire we;

//wire [11:0] address_r, address_w;

wire [6:0] d_out;

// cursor

wire cursor_on;

// delayed pixel count

reg [9:0] pixel_x1_reg, pixel_x2_reg, pixel_x3_reg;

reg [9:0] pixel_y1_reg, pixel_y2_reg, pixel_y3_reg;

// object output signals

wire [2:0] font_colour, cursor_colour;

// instantiate character ROM

character_rom character_rom_block_unit

(.clk(clk),

.address(rom_address),

.data(font_word));

// registers

always @(posedge clk)

begin

pixel_x1_reg <= pixel_x;

pixel_x2_reg <= pixel_x1_reg;

pixel_x3_reg <= pixel_x2_reg; //******

pixel_y1_reg <= pixel_y;

pixel_y2_reg <= pixel_y1_reg;

pixel_y3_reg <= pixel_y2_reg; //******

write_data <= ascii_in;

write_addr <= write_row_address * `MAXIMUM_H + write_bit_address;

read_addr <= (pixel_y >> 4) * `MAXIMUM_H + (pixel_x >> 3);

read_data <= ram[read_addr];

if (w_enable)

begin

ram[write_addr] <= write_data;

write_bit_address <= (write_bit_address == `MAXIMUM_H-1) ? 0 : write_bit_address + 1;

write_row_address <= (write_bit_address == `MAXIMUM_H-1) ? (write_row_address == `MAXIMUM_V-1) ? 0 : write_row_address + 1 : write_row_address;

end

end

// tile RAM read

assign char_address = read_data;

// character ROM

assign row_address = pixel_y[3:0];

assign rom_address = {char_address, row_address};

// use delayed coordinate to select a bit

assign bit_address = pixel_x3_reg[2:0];

assign font_bit = font_word[~bit_address];

// object signals

// green over black

assign font_colour = (font_bit) ? 3'b101 : 3'b000;

assign cursor_colour = 3'b010;

// use delayed coordinate for comparison

assign cursor_on = (pixel_y3_reg [8:4] == write_row_address) &&

(pixel_x3_reg [9:3] == write_bit_address);

// rgb multiplexing circuit

always @*

if (~text_on)

//(text_on)

text_rgb = 3'b000;

else if (cursor_on)

text_rgb = cursor_colour;

else

text_rgb = font_colour;

endmodule

module top_vga_display_controller(clk, reset, w_enable, ascii_in, h_sync, v_sync, rgb);

input clk, reset, w_enable;

input wire [6:0] ascii_in;

output h_sync, v_sync;

output wire [2:0] rgb;

// signal declaration

wire [9:0] pixel_x, pixel_y;

wire video_on, pixel_tick; ///

reg [2:0] rgb_reg;

wire [2:0] rgb_next; ////

// body

// instantiate vga_sync circuit

vga_sync vga_syncronization_block_unit

(.clk(clk),

.reset(reset),

.h_sync(h_sync),

.v_sync(v_sync),

.video_on(video_on),

.p_tick(pixel_tick),

.pixel_x(pixel_x),

.pixel_y(pixel_y));

// font generation circuit

text_pixel_generation_circuit text_pixel_generation_block_unit

(.clk(clk),

.reset(reset),

.text_on(video_on),

.w_enable(w_enable),

.ascii_in(ascii_in),

.pixel_x(pixel_x),

.pixel_y(pixel_y),

.text_rgb(rgb_next));

// rgb buffer

always @(posedge clk)

if (pixel_tick)

rgb_reg <= rgb_next;

assign rgb = rgb_reg;

endmodule

module VGA3 (clk, reset, ps2_data, ps2_clk, h_sync, v_sync,rgb);

input clk, reset;

input ps2_data, ps2_clk;

output h_sync, v_sync;

output wire [2:0] rgb;

wire [6:0] ascii_in;

wire write_disable, write_enable;

//reg Transmit_on;

//localparam Enter_key = 8'h0A;

// body

// instantiate keyboard scan code circuit

keyboard_code keyboard_controller_block_unit

(.clk(clk),

.reset(reset),

.ps2_data(ps2_data),

.ps2_clk(ps2_clk),

.read_code(write_disable),

.write_enable(write_enable),

.ascii_code(ascii_in));

// instantiate top level vga display circuit

top_vga_display_controller vga_display_controller_block_unit

(.clk(clk),

.reset(reset),

.w_enable(write_disable),

.ascii_in(ascii_in),

.h_sync(h_sync),

.v_sync(v_sync),

.rgb(rgb));

/*

always @*

if(ascii_in == Enter_key)

Transmit_on = 1;

else

Transmit_on = 0;

*/

//assign write_disable = ~Transmit_on;

assign write_disable = ~write_enable;

endmodule