backspace and enter key, reset VGA in verilog HDL?

There is one typical syntax mistake commonly done.

assign h_end = (h_count_reg == (HD+HF+HB+HR-1));

You use == what is a logical equality its result can be unknown, you should better use === what is case equality and will only result in true or false

assign h_end = (h_count_reg === (HD+HF+HB+HR-1));

Next thing. inside an always construct, you better use the non blocking assignment <= instead of the single =.

Your code shows only the the video synchronisation signals, but no video information itself. No RGB signal shown, i assume this must be done somewhere else where the video_on signal is use ...