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sleh's avatar
sleh
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1 month ago

Avalon-ST configuration with Agilex 3 fails

Hi, I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. Thi...
Configuration
Programmable Logic Device
FvM's avatar
FvM
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1 month ago

Hi Samuel, 

maybe I missed something, but I don't see signal names for LA traces.

Also post #1 is talking about PS configuration method while you later mention AVST.

Regards Frank

P.S.: Sorry for confusion. My image viewer cut left margin. 

What is the criterion for deasserting valid at the end of failing cycle?

sleh's avatar
sleh
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1 month ago

Hi Frank,

We have been using Cyclon and Agilex FPGAs for many years. These are programmed via PS from the host CPU using SPI. Unfortunately, Agilex does not support PS, and we do not want to use an additional CPLD or QSPI flash for configuration. Therefore, I am trying to emulate a kind of passive serial programming based on AVST, see attached image.

The programming generally works, but fails the first time after power-up. I suspect that there is a problem even before programming, as the nSTATUS pin follows the timing of nCONFIG, which is unexpected, see attached image.