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sleh's avatar
sleh
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1 month ago

Avalon-ST configuration with Agilex 3 fails

Hi, I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. Thi...
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Programmable Logic Device
FvM's avatar
FvM
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1 month ago

Hi Samuel, 

maybe I missed something, but I don't see signal names for LA traces.

Also post #1 is talking about PS configuration method while you later mention AVST.

Regards Frank

P.S.: Sorry for confusion. My image viewer cut left margin. 

What is the criterion for deasserting valid at the end of failing cycle?

  • sleh's avatar
    sleh
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    1 month ago

    Hi Frank,

    We have been using Cyclon and Agilex FPGAs for many years. These are programmed via PS from the host CPU using SPI. Unfortunately, Agilex does not support PS, and we do not want to use an additional CPLD or QSPI flash for configuration. Therefore, I am trying to emulate a kind of passive serial programming based on AVST, see attached image.

    The programming generally works, but fails the first time after power-up. I suspect that there is a problem even before programming, as the nSTATUS pin follows the timing of nCONFIG, which is unexpected, see attached image.

    • FvM's avatar
      FvM
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      1 month ago

      Hi Samuel,

      thanks for the schematic, I got the idea of AVST Emulation now. Can't say if undelsyed nSTATUS indicates faulty behaviour, the delay might simply depend on previous device state and be different for first configuration after POR. Seeing neither CONFIG_DONE (config success) nor nSTATUS (config error) asserted means primarily that the device is waiting for more data, I think.

      Regards Frank

      • sleh's avatar
        sleh
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        1 month ago

        Hi Frank,

        Thank you for your reply. I am sure that the data transfer is complete and correct:

        • The programming generally works, except after a restart.
        • I run the same code on my CPU, regardless of whether the system was started by a power cycle or a reset.
        • The output of the logic analyzer shows that the data is complete.
        • I changed the code so that I send a zero (valid high) at the end of the transfer. I would have expected nStatus to signal an error or ready to go low.

        It seems to me that the FPGA is in a state that can only be exited by a second programming.

        Something else that is unexpected is the behavior of “ready,” see attached image. In the first programming cycle (after power-up), it only goes low once. In all subsequent programming cycles, it goes low many times. Shouldn't programming with the same rbf file be deterministic?

        Regards Samuel