Audio processor with verilog

Question

Hi,  I've been doing this project for about a year now and after so many ups and downs i've reached a point where everything seems right but warnings appear that I've got no clue how to amend. this project is meant to receive series of digital data coming out of an electric guitar, embed them into 12-bit parallel packets, and then apply the desired effect previously considered. all the operations are done in time-domain meaning that e.g i have chosen to use a ram and addressing and counting to implement a Delay effect instead of using a Z transform process,a discrete-time filter. the approaches differ but the result must be the same. anyways here is the code : module Multieffect(din1,Audio_out,Clk1,control,Reset,rsta,wea);
input din1;
input Clk1,Reset,wea;
input control;
input rsta;
output Audio_out;
reg t1;
reg t2,t3,REG_0;
wire clkdv;
wire Clk2x;
wire SIPORAM,CROMMUX,PROMMUX,ECHOREG,MUXRAM,RAMREG,REG0,REGD,ADDED_AUDIO,SUB_AUDIO,muxtoPISO;
wire clk0;
reg ADDRESS;
integer k=0;
assign ECHOREG=1000;
dcm1 u(.CLKIN_IN(Clk1),.RST_IN(Reset),.CLKDV_OUT(clkdv),.CLKIN_IBUFG_OUT(),.CLK0_OUT(clk0),.CLK2X_OUT(Clk2x),.LOCKED_OUT());
SIPO u0(.din(din1),.clk(clkdv),.reset(Reset),.dout(SIPORAM));
CHORUSROM u1(.out(CROMMUX),.clk(Clk2x));
PHASERROM u2(.out(PROMMUX),.clk(Clk2x));
always @(posedge clkdv)
begin
if (k==4094)
ADDRESS &lt;=0;
else
ADDRESS &lt;= ADDRESS + 1'b1 ;
k&lt;=k+1;
end 
mux4_1 u3(.din_0(ECHOREG),.din_1(CROMMUX),.din_2(PROMMUX),.din_3(PROMMUX),.sel(control),.mux_out(MUXRAM));
SDP_BRAM u4(.clka(clkdv),.wea(wea),.addra(ADDRESS),.dina(SIPORAM),.clkb(Clk2x),.rstb(rsta),.addrb(MUXRAM),.doutb(RAMREG));
AddSub u5 (.clk(clk0),.ce(1'b1),.s(ADDED_AUDIO),.a(RAMREG),.b(RAMREG));
AddSub2 u6 (.clk(clk0),.ce(1'b1),.s(SUB_AUDIO),.a(RAMREG),.b(RAMREG));
mux_4_1_2 u7(.in10(ADDED_AUDIO),.in11(ADDED_AUDIO),.in12(ADDED_AUDIO),.in13(SUB_AUDIO),.sel1(control),.mux_out1(muxtoPISO));
PISO u8(.clk(clk0),.ld(1'b1),.shift(1'b1),.pi(muxtoPISO),.q(Audio_out));
 and these lines are the warnings I get :  WARNING:HDLCompiler:1499 - "C:\Users\YJM\Multi.effect\SDP_BRAM.v" Line 39: Empty module &lt;SDP_BRAM&gt; remains a black box. WARNING:Xst:2999 - Signal 'Mem', unconnected in block 'CHORUSROM', is tied to its initial value. WARNING:Xst:3035 - Index value(s) does not match array range for signal &lt;Mem&gt;, simulation mismatch. WARNING:Xst:2999 - Signal 'Mem1', unconnected in block 'PHASERROM', is tied to its initial value. WARNING:Xst:3035 - Index value(s) does not match array range for signal &lt;Mem1&gt;, simulation mismatch. WARNING:Xst:1290 - Hierarchical block &lt;u7&gt; is unconnected in block &lt;Multieffect&gt;.    It will be removed from the design. WARNING:Xst:1710 - FF/Latch &lt;out_0&gt; (without init value) has a constant value of 0 in block &lt;PHASERROM&gt;. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;out_9&gt; (without init value) has a constant value of 0 in block &lt;PHASERROM&gt;. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;out_10&gt; (without init value) has a constant value of 0 in block &lt;PHASERROM&gt;. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;out_11&gt; (without init value) has a constant value of 0 in block &lt;PHASERROM&gt;. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1290 - Hierarchical block &lt;u7&gt; is unconnected in block &lt;Multieffect&gt;.    It will be removed from the design.   there are submodules also and .txt files but i think it's better i upload them step by step. it might get a too messy to read first post!

altera_forum · Answer

1. you're using XST - that is a Xilinx piece of software for compiling into Xilinx devices - this is an altera forum (xilinx's competitor)

2. you havent posted the code - all you have posted is a netlist. I dont know what half the modules are meant to do.

3. Have you got a testbench for the code?

4. The warnings are several things

- Whatever SDP_BRAM is, there is no functionality inside it - hence the compiler is treating it as a black box

- The warnings for mem and mem1 should be fairly self explanitory (mem and mem1 are never assigned values. And then whatever the index is outside of the range of what it's indexing into)

- U7 is unconnected and will be removed from the design

- The trimming warnings are because there are some signals that drive this signal stuck at '0', hence these registers are removed because they are redundant (they are also stuck at 0).

altera_forum · Answer

thanks for your reply.

1. I don't have an FPGA board yet. I just used the xilinx ISE to synthesize my project. the xilinx forum required me to already have the board in order to register.So I defected to altera forums! but do they differ ? verilog is verilog everywhere.

2.I made amendments in the first post and uploaded some of the modules and then some with this one.

3. the testbench result was pure XXXXXXXX...s.

4.SDP_BRAM is an IP core module. please share your idea about the other errors now that the other submodules are available to study.

altera_forum · Answer

If you have created IP core modules in ISE, you cannot use them in altera. I highly suggest you download and use Quartus if you are going to target altera parts.

The mem index range warnings are because you used an integer (32 bit value) to index into the mem that only has a 10 bit address. Same with the Phase

If the testbench is pure XXXXs, then you have some driver or initialisation problems somewhere - this is your job to debug.

altera_forum · Answer

I don't completely understand what you are referring to about mem index.e.g mem in phaserom is a rack of 400 12-bit registers.  the only 32 bit value here is the k and I think it's got nothing to do with the size of the registers unless i am wrong or misunderstood you. module PHASERROM(out,clk);
    output reg out;
    input clk;
	 integer k=0;
	 reg  Mem1;
	 initial $readmemb("phaser.txt",Mem1); 
	 always @ (posedge clk)
	   begin
	     out&lt;= Mem1;
		  k=k+1;
		  if(k==400)
		    k=0;
	   end	
endmodule

altera_forum · Answer

I don't think I quite understand you on the mem index subject ... What integer is 32-bit value while it is addressed in 10 bits? there are no 10 bit values. it is 12. I checked but couldn't figure it out. would you be more precise ?

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Audio processor with verilog

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