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Altera_Forum
Honored Contributor
11 years agoAudio processor with verilog
Hi, I've been doing this project for about a year now and after so many ups and downs i've reached a point where everything seems right but warnings appear that I've got no clue how to amend. thi...
Altera_Forum
Honored Contributor
11 years agoI replaced integer k with a reg [9:0] k but nothing changed in the warning section.
matter of fact i realized that many of these warnings are better left ignored. yet the disappearance of u7 might be a warning from the program but it's sure an ERROR for me. I looked up for the same problems and found out the ISE chooses to remove this block because it thinks there is no difference after all cause in its view, u7 does nothing but wasting time and space. why is that so ?