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Altera_Forum's avatar
Altera_Forum
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11 years ago

Audio processor with verilog

Hi, I've been doing this project for about a year now and after so many ups and downs i've reached a point where everything seems right but warnings appear that I've got no clue how to amend. thi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Have you got a clock/reset/enable or stuck at zero?

You can check the RTL view to see what has actually been synthesised.