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Altera_Forum
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15 years ago

Asynch Design Challenge

After all the chat in this thread (http://www.alteraforum.com/forum/showthread.php?t=26151)regarding glitching in the outputs of asynchronous logic, I thought I would post the following challenge for people to discuss:

Design a circuit to divide a clock by 3, keeping a 1:1 mark to space ratio and to start working instantly with no delay. i.e. using a PLL isn't allowed. I will allow a reset pulse to get things going in simulation in a known state but a real implementation shouldn't need it.

Extra bonus points for using the smallest amount of LEs.

http://farm5.static.flickr.com/4131/5144985871_0171bb6cc5_z.jpg

I'm rather proud of my solution which only uses three LEs (though it does have drawbacks). I'll post it in a couple of days so people can have a think about it first.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    For clarity, we should distinguish between synchronous register (or FF) and asynchronous latch (which is implemented by Quartus mostly as logic loop).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Ok, I've received my new power supply so I'm up and running again.

    This is my latchless design which requires three LUTs: 

    module asynchclockdiv (
    input wire clkin,
    input wire reset,
    output wire clkout
);
    wire q2, q1, q0 /* synthesis keep */;
    assign q0 = ((clkin & !q2) | (clkin & q0) | (!q2 & q0)) & !reset;
    
    assign q1 = ((!clkin & q1) | (!clkin & q0) | (q1 &q0)) & !reset;
    
    assign q2 = (!clkin & q2 & q0) | (clkin & q2 & !q0) | (clkin & q1 & q0) | (q2 & q1);
    assign clkout = q2;
endmodule
    It operates as a 6 state machine with the other two states transforming into the normal modes so it should always power up and start working.

    It isn't a design I would recommend for anything other than an exercise as it is very easy to break. For example, if q2 was gated with the reset line like q0 and q1 then it no longer fits into a single LE, glitching occurs and the result isn't correct.

    jakobjones solution makes me think it may be possible to do an async design with two LEs also. I will have to have a think about that.