Asynch Design Challenge

Ok, I've received my new power supply so I'm up and running again.

This is my latchless design which requires three LUTs:

module asynchclockdiv (
    input wire clkin,
    input wire reset,
    output wire clkout
);
    wire q2, q1, q0 /* synthesis keep */;
    assign q0 = ((clkin & !q2) | (clkin & q0) | (!q2 & q0)) & !reset;
    
    assign q1 = ((!clkin & q1) | (!clkin & q0) | (q1 &q0)) & !reset;
    
    assign q2 = (!clkin & q2 & q0) | (clkin & q2 & !q0) | (clkin & q1 & q0) | (q2 & q1);
    assign clkout = q2;
endmodule

It operates as a 6 state machine with the other two states transforming into the normal modes so it should always power up and start working.

It isn't a design I would recommend for anything other than an exercise as it is very easy to break. For example, if q2 was gated with the reset line like q0 and q1 then it no longer fits into a single LE, glitching occurs and the result isn't correct.

jakobjones solution makes me think it may be possible to do an async design with two LEs also. I will have to have a think about that.