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Altera_Forum's avatar
Altera_Forum
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11 years ago

arriaII GX LVDS clock input and 1.8V IO

I have two questions.

(1) LVDS clock input

I am planning to use EP2AGX65DF29C4.

I set VCCIO=2.5V,VCCPD=2.5V in BANK3A.

CLK6,4 input LVDS clock.

（This is consulting the circuit of the evaluation board of Altera.）

When I set VCCIO=1.8V,VCCPD=2.5V in BANK8A,

Is it possible that I use CLK14,12 as LVDS clock input?

(2)1.8V IO

I am planning to use DVI Transmitter(TFP410,TI)

I use this 1.8V Signal Levels.

When I connect TFP410 with bank8A of EP2AGX65DF29C4,Should I set VCCIO=1.8V and VCCPD=2.5V?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    1) Yes, you can drive LVDS signal pairs into I/O banks powered at 1.8V. (VCCPD=2.5V as you pointed out).

    2) Yes, those voltage settings are correct.

    Can I suggest that you (as I did to confirm these answers) use Quartus to help you? Put a small design together, make the pin location assignments and signal types that you want and run it through the tools. Quartus will quickly tell you if you're trying something your target device doesn't support.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    1) Yes, you can drive LVDS signal pairs into I/O banks powered at 1.8V. (VCCPD=2.5V as you pointed out).

    2) Yes, those voltage settings are correct.

    Can I suggest that you (as I did to confirm these answers) use Quartus to help you? Put a small design together, make the pin location assignments and signal types that you want and run it through the tools. Quartus will quickly tell you if you're trying something your target device doesn't support.

    Cheers,

    Alex

    --- Quote End ---

    Thank you, Alex-san

    I have more question.

    I am planning to use EP2AGX65DF29C4.

    I am planning to use DDR3 in BANK7A and BANK4A.

    When I set VCCIO=1.5V(for DDR3 SSTL 15 class I),VCCPD=2.5V in BANK7A ,

    Is it possible that I use CLK13,15 as LVDS clock input?

    When I set VCCIO=1.5V(for DDR3 SSTL 15 class I),VCCPD=2.5V in BANK4A ,

    Is it possible that I use CLK7,5 as LVDS clock input?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Yes, that all appears to be possible.

    Again, as I said before - and as I did before - put together a small project and test the settings you want. That's what I did and that gave me the answer...

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thank you ,

    Alex-san,

    I made small project.

    I assigned DDR3(SSTL 15 class I)in bank7A and bank 4A.

    I assigned LVDS clks to CLK13,15(bank7A) and CLK7,5(bank4A).

    And I confirmed that compile error doesn't occur.