Altera_ForumHonored Contributor10 years agoarriaII GX LVDS clock input and 1.8V IO I have two questions. (1) LVDS clock input I am planning to use EP2AGX65DF29C4. I set VCCIO=2.5V,VCCPD=2.5V in BANK3A. CLK6,4 input LVDS clock. (This is consulting the circuit of...Show More
Recent DiscussionsDK-DEV-AGI027-RA QSPI Verification FailsCyclone 5 SoC FPGA Bank Supply PrerequisiteAGILEX 5 Migration issueTo INTEL - Request for Compliance Data from Analog Devices, IncArria 10 GX RX max intra-differential pair skew