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1) Yes, you can drive LVDS signal pairs into I/O banks powered at 1.8V. (VCCPD=2.5V as you pointed out).
2) Yes, those voltage settings are correct.
Can I suggest that you (as I did to confirm these answers) use Quartus to help you? Put a small design together, make the pin location assignments and signal types that you want and run it through the tools. Quartus will quickly tell you if you're trying something your target device doesn't support.
Cheers,
Alex
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Thank you, Alex-san
I have more question.
I am planning to use EP2AGX65DF29C4.
I am planning to use DDR3 in BANK7A and BANK4A.
When I set VCCIO=1.5V(for DDR3 SSTL 15 class I),VCCPD=2.5V in BANK7A ,
Is it possible that I use CLK13,15 as LVDS clock input?
When I set VCCIO=1.5V(for DDR3 SSTL 15 class I),VCCPD=2.5V in BANK4A ,
Is it possible that I use CLK7,5 as LVDS clock input?
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