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Altera_Forum
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11 years ago

arriaII GX LVDS clock input and 1.8V IO

I have two questions. (1) LVDS clock input I am planning to use EP2AGX65DF29C4. I set VCCIO=2.5V,VCCPD=2.5V in BANK3A. CLK6,4 input LVDS clock. （This is consulting the circuit of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you ,

Alex-san,

I made small project.

I assigned DDR3(SSTL 15 class I)in bank7A and bank 4A.

I assigned LVDS clks to CLK13,15(bank7A) and CLK7,5(bank4A).

And I confirmed that compile error doesn't occur.