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jozephka99's avatar
jozephka99
Icon for Contributor rankContributor
4 years ago

Arria10 SoC Devkit FPGA UART Guide

Hi,
I’m trying to get worked Arria10 SoC Devkit’s FPGA side UART in FPGA side only. It seems that it is connected to HPS’ shared I/O pins. These pins have multiple signals and they must be choosen with a HPS pin mux select. (refer to: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/arria-10/arria10hps.xls). I search a bit and although not sure the pin mux selection performs in platform designer. So I create a system design with a HPS Arria10 IP. But after that I’m gonna be confused a little bit. When I’m selecting the UART1 from the advence FPGA placement tab, IP creates a UART signal, not just RX/TX a bunch of signals (ready signal, send req, …). But I’m not sure how can I use them. Am I doing rigth thing to use FPGA side UART? In FPGA side UART should just be RX/TX? What should I do now?
Any help will be thankful.

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    You chose "To FPGA" so the conduit is including those extra signals. I think you have to enable the UART under "To HPS I/Os". Or if you indeed want the UART to go to the FPGA, you don't have to use extra signals you don't need.

  • jozephka99's avatar
    jozephka99
    Icon for Contributor rankContributor
    4 years ago

    I choose uart1 and uart0 to the FPGA. I exported the uart signals. Then I connected these signals in my logic. But when I connect the uart port with a serial communication program (like minicom) on computer, i see:

    "U-Boot 2014.10 (May 01 2016 - 08:22:23)

    CPU : Altera SOCFPGA Arria 10 Platform
    BOARD : Altera SOCFPGA Arria 10 Dev Kit
    DRAM: WARNING: Caches not enabled
    SOCFPGA DWMMC: 0
    Fail: read msel=2
    FPGA: Init failed with error code -1
    INFO : Skip relocation as SDRAM is non secure memory
    Reserving 2048 Bytes for IRQ stack at: ffe2db10
    data abort
    pc : [<ffe00b1a>] lr : [<ffe01d4d>]
    sp : ffe3bf00 ip : 0000001c fp : 00000001
    r10: ffd02078 r9 : ffe3bf60 r8 : ffe00054
    r7 : ffe20b60 r6 : ffe3c000 r5 : 00000000 r4 : ffffd000
    r3 : ffcfb000 r2 : 00000002 r1 : 00000001 r0 : 00000001
    Flags: nzcv IRQs off FIQs off Mode SVC_32
    Resetting CPU ..."

    I don't get it. I don't send this messages. If I routed the uart0 and uart1 to FPGA and if I don't send these messages, who can access the uart port and send them? If the hps send them, then I couldn't routed the uart to fpga. How can prevent it or connect the uart to the fpga in right way. Addition to this am I gonna do pin assignment for the exported uart signal, or the hps ip automaticaly do it?

  • jozephka99's avatar
    jozephka99
    Icon for Contributor rankContributor
    4 years ago

    No one knows about it? Really? No one use UART in this board I guess... Intel employees... Why the documentation about this expensive board is very awful. I don't get it at all.