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jozephka99
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4 years ago

Arria10 SoC Devkit FPGA UART Guide

Hi, I’m trying to get worked Arria10 SoC Devkit’s FPGA side UART in FPGA side only. It seems that it is connected to HPS’ shared I/O pins. These pins have multiple signals and they must be choosen w...
jozephka99's avatar
jozephka99
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4 years ago

I choose uart1 and uart0 to the FPGA. I exported the uart signals. Then I connected these signals in my logic. But when I connect the uart port with a serial communication program (like minicom) on computer, i see:

"U-Boot 2014.10 (May 01 2016 - 08:22:23)

CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
Fail: read msel=2
FPGA: Init failed with error code -1
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe2db10
data abort
pc : [<ffe00b1a>] lr : [<ffe01d4d>]
sp : ffe3bf00 ip : 0000001c fp : 00000001
r10: ffd02078 r9 : ffe3bf60 r8 : ffe00054
r7 : ffe20b60 r6 : ffe3c000 r5 : 00000000 r4 : ffffd000
r3 : ffcfb000 r2 : 00000002 r1 : 00000001 r0 : 00000001
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ..."

I don't get it. I don't send this messages. If I routed the uart0 and uart1 to FPGA and if I don't send these messages, who can access the uart port and send them? If the hps send them, then I couldn't routed the uart to fpga. How can prevent it or connect the uart to the fpga in right way. Addition to this am I gonna do pin assignment for the exported uart signal, or the hps ip automaticaly do it?