Arria10 FPGA transciever FEC specifications

Question

Hello,

I am looking for specifications of the FEC used in the Arria10 FPGA transciever, more specifically its theoretical performance (maximum BER at input for error-free output, burst error size that would defeat error correction, etc.). All the information I could find is here: Intel® Arria® 10 Transceiver PHY User Guide, 2.6.2. It says the FEC 64b/66b but that is it. Where can I find more information on this?

Thank you,
--
RD

skbeh · Accepted Answer

Hi RomainA10 transceiver Native PHY with FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10e12.Refer section 2.9. Other Protocolshttps://www.intel.com/content/www/us/en/docs/programmable/683617/

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Arria10 FPGA transciever FEC specifications

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