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Romain_D
New Contributor
New ContributorArria10 FPGA transciever FEC specifications
Hello,
I am looking for specifications of the FEC used in the Arria10 FPGA transciever, more specifically its theoretical performance (maximum BER at input for error-free output, burst error size ...
Hi Romain
A10 transceiver Native PHY with FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10e12.
Refer section 2.9. Other Protocols
https://www.intel.com/content/www/us/en/docs/programmable/683617/
Romain_DNew Contributor
New ContributorHi @skbeh ,
Thank you for the intel. I found what I was looking for by following a resource mentioned mentioned in the document you linked:
"The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE 802.3ap-2007"
IEEE 802.3ap-2007 contained everything I was looking for.
Thank you,
--
RD
