Romain_D
New Contributor
3 years agoArria10 FPGA transciever FEC specifications
Hello,
I am looking for specifications of the FEC used in the Arria10 FPGA transciever, more specifically its theoretical performance (maximum BER at input for error-free output, burst error size ...
- 3 years ago
Hi Romain
A10 transceiver Native PHY with FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10e12.
Refer section 2.9. Other Protocols
https://www.intel.com/content/www/us/en/docs/programmable/683617/