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Altera_Forum's avatar
Altera_Forum
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15 years ago

Arria PLL Reset

I have a LVDS Reciever running at parallel clock of 162MHz and a 4:1 serialisation.

When I use the altlvds megafunction with no reset input and only the "PLL_Locked" output for signaltap use, it works correctly and copes with input async connection, clock interruptions and almost anything I can do to disrupt the data flow. Recovery is fast and correct.

However under the design rules I was given, I have to initiate a PLL Reset when I detect a loss of clock. This is when I have problems both on power on starts and occasional clock interruption.

Does Altera have a working example of how to best impliment a LVDS or PLL reset that will cope with async. clock connection and data loss.

I already have an effective and accurate bit alignment system that periodically checks and corrects the bit alignment if required (this is triggered by a specific string of data that occurs periodically).

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    HI,

    Thanks for the prompt reply.

    In your opinion, do I really need to use DPA when the parallel data frequency is 162MHz and the LVDS ratio is only 4:1 ?

    The system is a single Arria GX on a main board transmitting to a single Cyclone III on a sub board. The data is processed on the sub board and transmitted back down to the main board by the Cyclone III to the Arria GX.

    The source clock for the entire system is a XO on the main board at 162MHz.

    The race lengths are controlled to be within +/-0.25mm between pairs and +/-0.1mm between traces in any pair.

    Thanks

    Brian Thompson