Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Arria PLL Reset

I have a LVDS Reciever running at parallel clock of 162MHz and a 4:1 serialisation. When I use the altlvds megafunction with no reset input and only the "PLL_Locked" output for signaltap use, it w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

HI,

Thanks for the prompt reply.

In your opinion, do I really need to use DPA when the parallel data frequency is 162MHz and the LVDS ratio is only 4:1 ?

The system is a single Arria GX on a main board transmitting to a single Cyclone III on a sub board. The data is processed on the sub board and transmitted back down to the main board by the Cyclone III to the Arria GX.

The source clock for the entire system is a XO on the main board at 162MHz.

The race lengths are controlled to be within +/-0.25mm between pairs and +/-0.1mm between traces in any pair.

Thanks

Brian Thompson