Honored ContributorI want to use several read and write masters to control ddr in arria 10, but I　can not fund the MPFE in the ip parameter setting. Does any know how to solve the problem?
Honored ContributorThat core is from a 3rd party vendor, Microtronix:
http://www.microtronix.com/fpga-ip-hd-video-products/fpga-ip-cores-development-solutions/avalon-multi-port-front-end All yours for only $2500. Another option would be to let Qsys build the interconnect to share the memory interface. I chose to build my own arbiter to share the Arria 10 memory controller outside of Qsys because I needed to be able to fine-tune the throughput performance and to have different access priorities. If you don't need that level of control then Qsys should be able to do what you need.Honored ContributorI think the OP is thinking about the hard MPFE that was in previous device families and on the HPS side in SoC devices.
But the rest of rsefton's response is correct. Qsys can manage the arbitration for you and you can set arbitration priorities for each master connected to the EMIF.Honored ContributorHard MPFE only support is hard memory controller in Cyclone/Arria V.
However, for user that like to connect 2 avalon master to 1 avalon slave in Arria 10 –> They can just connect the connection directly in QSYS (connect the dot). When multiple masters contend for access to a slave, Qsys automatically inserts arbitration logic, which grants access in fairness-based, round-robin order. You can found the detail in Quartus handbook -> Qsys Interconnect -> Memory mapped Inteface ->Arbitration https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf page 459 (This message was posted on behalf of Intel Corporation)
