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Altera_Forum
Honored Contributor
Honored ContributorArria 10 DDR multi-port front end not suported?
I want to use several read and write masters to control ddr in arria 10, but I　can not fund the MPFE in the ip parameter setting. Does any know how to solve the problem?
Altera_ForumHonored Contributor
Honored ContributorI think the OP is thinking about the hard MPFE that was in previous device families and on the HPS side in SoC devices.
But the rest of rsefton's response is correct. Qsys can manage the arbitration for you and you can set arbitration priorities for each master connected to the EMIF.
