Forum Discussion
Altera_Forum
Honored Contributor
9 years agoArria 10 DDR multi-port front end not suported?
I want to use several read and write masters to control ddr in arria 10, but I can not fund the MPFE in the ip parameter setting. Does any know how to solve the problem?
Altera_Forum
Honored Contributor
9 years agoThat core is from a 3rd party vendor, Microtronix:
http://www.microtronix.com/fpga-ip-hd-video-products/fpga-ip-cores-development-solutions/avalon-multi-port-front-end All yours for only $2500. Another option would be to let Qsys build the interconnect to share the memory interface. I chose to build my own arbiter to share the Arria 10 memory controller outside of Qsys because I needed to be able to fine-tune the throughput performance and to have different access priorities. If you don't need that level of control then Qsys should be able to do what you need.