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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria 10 DDR multi-port front end not suported?

I want to use several read and write masters to control ddr in arria 10, but I　can not fund the MPFE in the ip parameter setting. Does any know how to solve the problem?
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hard MPFE only support is hard memory controller in Cyclone/Arria V.

However, for user that like to connect 2 avalon master to 1 avalon slave in Arria 10 –> They can just connect the connection directly in QSYS (connect the dot). When multiple masters contend for access to a slave, Qsys automatically inserts arbitration logic, which grants access in fairness-based, round-robin order.

You can found the detail in Quartus handbook -> Qsys Interconnect -> Memory mapped Inteface ->Arbitration

https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf page 459

(This message was posted on behalf of Intel Corporation)