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Altera_Forum's avatar
Altera_Forum
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16 years ago

Arbitrary Waveform

Hi,

I need to improve the Linearisation of a VCO, For that i need to provide arbitrary waveform see attached between voltage 0 to 5VDC (it is like Triangle waveform but not the same).

I think to insert the values to a PROM (look-up table) and with D/A the CPLD/FPGA will produce the waveform.

Please advice.

Regards,

Doron

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, it surely works. To select the design details, a specification for resolution, accuracy, speed would be useful. You also didn't mention what's the source of the control signal.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Yes, it surely works. To select the design details, a specification for resolution, accuracy, speed would be useful. You also didn't mention what's the source of the control signal.

    --- Quote End ---

    The period of the waveform is 250uSec and it is cyclic.

    I would like that the Altera device will provide will provide this waveform or to put a D/A at the output of the device.

    Can CPLD Do the the job ?

    Please advice which simplified device will do the job ?

    Thanks,

    Doron
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    if the voltage waveform is between 0VDC to +5VDC then lets calculate the resolution with 2^8:

    5000mV/(2^8) = 19.5mV.

    This the voltage Resolution.

    Let me know if you need more data.

    Thanks,

    Doron
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You will need a D/A converter on the board - FPGA only have digital output pins.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, I took as granted, that an external DAC would be necessary with any programmable logic device. 8-Bit amplitude resolution defines the number of data bits, a second design parameter is the number of LUT entries.

    A CPLD must implement a ROM in logic cells, most smaller CPLD won't have enough resources to represent an arbitrary look-up table. But the logic is minimized by the design compiler, in some cases it may be sufficient. I suggest to define the table coding and let Quartus try to fit it to different CPLD.

    FPGAs have internal memory, that can be used as a ROM, so it's much easier with it. As another point, at low and medium speed, a PWM or SD modulator 1-Bit DAC can be used with a low-pass to generate the waveform.