Arbitrary Waveform

Yes, I took as granted, that an external DAC would be necessary with any programmable logic device. 8-Bit amplitude resolution defines the number of data bits, a second design parameter is the number of LUT entries.

A CPLD must implement a ROM in logic cells, most smaller CPLD won't have enough resources to represent an arbitrary look-up table. But the logic is minimized by the design compiler, in some cases it may be sufficient. I suggest to define the table coding and let Quartus try to fit it to different CPLD.

FPGAs have internal memory, that can be used as a ROM, so it's much easier with it. As another point, at low and medium speed, a PWM or SD modulator 1-Bit DAC can be used with a low-pass to generate the waveform.