Anyone ported AN532 PCIe to Arria2GX dev kit?

Hope it might help some one like me.

Here I am attaching working PCI - SOPC reference design for Arria II GX Dev kit.

Hey Frederik

Having same problem with porting AN532 to Arria II GX. It would be great if you could share the wrapper module and some tips.

Ok, I do see the device under linux with lspci.

Thanks a lot!

Hi Peter,

I just found AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. That helps. I found the reconfig block in the Megawizard. I will test it now.

Regards,

Frederik

Hi Peter,

tahnk you for the answer.

My design still doesn't work. I read that i need the reconfig block but it isn't generated and i can't choose PCI reconfig in the Megawizard from the SOPC builder.

Where did you get yours? Maybe that's a problem with Quartus 10.0? It's "N/A" - not available. If i start the Megawizard manually the option is available.

The pcie reference clock from the motherboard is 100 MHz. Do you confirm that a division by 3 works? I ask, because it's less that 37MHz that you mentioned in your wrapper.

Regards,

Frederik

Frederik,

Here is my wrapper. Mine is a x4 lanes PCIe design. I have also re-defined the LCD connector so that I can connect some Logic Analyser probes to check out a few things. You could of course use the SignalTap II to probe your design.

regards,

Peter

Hello Peterch,

ok, that is what i needed to know.

I'm writing the wrapper taking the <sopc>_inst.vhd . I will tie every unused signal to '0', but test_in in that way you showed obove. Is that ok?

Maybe you could post your working wrapper. I think others would appreciate it.

Regards,

Frederik

Frederik,

Quartus 10 is fine. I have been using that for sometime.

I did write a wrapper in vhdl with the sopc component as an instantiation.

You can add the reconfig module in the wrapper and also the reconfig_clk generator.

The original AN532 did have a verilog wrapper which you can download from the dev kit area, and that will give you some idea.

Regards,

Peter

Hi PeterCH,

what I tried to do is to leave out the test-signal and to connect the sopc-system directly to the FPGA-pins. Is that wrong? Did you write a wrapper around the system?

I realized that in AN532 a wrapper is needed to tie the reconfig-inputs to fixed values. I don't have a reconfig-block in my system. I am trying Quartus 9.1.

I just want to create a very small system to do some evaluation on it. That consumes a lot of time.

Thanks in advance,

Frederik

Frederik,

All inputs at the top level can be left unconnected. In VHDL, just declare a signal called gxb_powerdown_pcie_compiler_0_sig and connect that to the vhdl instantiation. DO the same for the other inputs.

You can use the 125Mhz clock output from the PCIe IP as your application input clock instead of the local_clock.

The MOST IMPORTANT signals is actually the test_in, see below:

test_in(39 downto 16) <= (others => '0');

-- selects the layer to output onto the test_out bus

test_in(15 downto 13) <= "000"; -- selects the Lane

test_in(12) <= '0'; -- selects VC

test_in(11 downto 8) <= "0010"; -- 0000 = Transaction Layer, 0010 = PHY-MAC outputs

test_in(7) <= '0'; -- Disable low power state negotiation

test_in(6 downto 5) <= "00"; -- b5 = completely disables compliance mode; never enter compliance mode

-- b6 = forces compliance mode.

test_in(4) <= '0'; -- Remote Boot mode

test_in(3) <= '1'; -- FPGA mode. Set to '1' for an FPGA implementation in order to appear compliant to other PCI Express components.

test_in(2) <= '0'; -- Descramble mode

test_in(1) <= '0'; -- Loopback Master

test_in(0) <= '0'; -- Simulation mode

Regards,

Peter