-- Description:
--				Converted from the verilog wrapper with the same name.
--				This file provides the top level for synthesis
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity SG_DMA_top is
	port( 
		local_rstn	: in	std_logic;
		local_clk	: in	std_logic;	-- 125 MHz?
		pcie_rstn	: in	std_logic;
		ref_clk		: in	std_logic;
		rx_in0		: in	std_logic;
		rx_in1		: in	std_logic;
		rx_in2		: in	std_logic;
		rx_in3		: in	std_logic;
		usr_sw		: in	std_logic_vector(7 downto 0);
		L0_led		: out	std_logic;
		alive_led	: out	std_logic;
		comp_led	: out	std_logic;
		lane_active_led	: out	std_logic_vector(3 downto 0);
		tx_out0		: out	std_logic;
		tx_out1		: out	std_logic;
		tx_out2		: out	std_logic;
		tx_out3		: out	std_logic;
		LCD_DATA	: out	std_logic_vector(7 downto 0);	-- goes out to LCD connector
		LCD_D_Cn	: out	std_logic;
		LCD_CSn	: out	std_logic;
		LCD_WEn	: out	std_logic
	);
end entity SG_DMA_top;


architecture rtl of SG_DMA_top is

signal alive_cnt : unsigned(24 downto 0);
signal any_rstn : std_logic;	-- active low reset
signal any_rst : std_logic;	-- active high reset

-- For debugging replaced registered outputs with wire. PC 17May2010
--  reg     [  3: 0] lane_active_led;

signal safe_mode : std_logic;
signal test_in : std_logic_vector(39 downto 0);		-- PC 14May10
signal test_out : std_logic_vector(63 downto 0);

-- added to support ALT_RECONFIG PC 18May2010
signal reconfig_fromgxb_sig : std_logic_vector(16 downto 0);
signal reconfig_togxb_sig : std_logic_vector(3 downto 0);
signal reconfig_clk_sig : std_logic;
--signal RefClk_Div2 : std_logic;
signal Count : integer range 0 to 2**4-1;	-- restricted to 4 bits. 2**4-1 or 15 is OK.
signal Div3 : std_logic;


signal clk125_out_pcie_compiler_0 : std_logic;

-- no connects
signal phystatus_ext_pcie_compiler_0_sig : std_logic;
signal pipe_mode_pcie_compiler_0_sig : std_logic;
signal rxdata0_ext_pcie_compiler_0_sig : std_logic_vector(7 DOWNTO 0);
signal rxdata1_ext_pcie_compiler_0_sig : std_logic_vector(rxdata0_ext_pcie_compiler_0_sig'range);
signal rxdata2_ext_pcie_compiler_0_sig : std_logic_vector(rxdata0_ext_pcie_compiler_0_sig'range);
signal rxdata3_ext_pcie_compiler_0_sig : std_logic_vector(rxdata0_ext_pcie_compiler_0_sig'range);
signal rxdatak0_ext_pcie_compiler_0_sig : std_logic;
signal rxdatak1_ext_pcie_compiler_0_sig : std_logic;
signal rxdatak2_ext_pcie_compiler_0_sig : std_logic;
signal rxdatak3_ext_pcie_compiler_0_sig : std_logic;
signal rxelecidle0_ext_pcie_compiler_0_sig : std_logic;
signal rxelecidle1_ext_pcie_compiler_0_sig : std_logic;
signal rxelecidle2_ext_pcie_compiler_0_sig : std_logic;
signal rxelecidle3_ext_pcie_compiler_0_sig : std_logic;
signal rxstatus0_ext_pcie_compiler_0_sig : std_logic_vector(2 DOWNTO 0);
signal rxstatus1_ext_pcie_compiler_0_sig : std_logic_vector(rxstatus0_ext_pcie_compiler_0_sig'range);
signal rxstatus2_ext_pcie_compiler_0_sig : std_logic_vector(rxstatus0_ext_pcie_compiler_0_sig'range);
signal rxstatus3_ext_pcie_compiler_0_sig : std_logic_vector(rxstatus0_ext_pcie_compiler_0_sig'range);
signal rxvalid0_ext_pcie_compiler_0_sig : std_logic;
signal rxvalid1_ext_pcie_compiler_0_sig : std_logic;
signal rxvalid2_ext_pcie_compiler_0_sig : std_logic;
signal rxvalid3_ext_pcie_compiler_0_sig : std_logic;
signal gxb_powerdown_pcie_compiler_0_sig : std_logic;
signal pll_powerdown_pcie_compiler_0_sig : std_logic;

COMPONENT sopc_sgdma is 
	PORT
	(
		-- 1) global signals:
		clk : IN STD_LOGIC;
		reset_n : IN STD_LOGIC;

		-- the_pcie_compiler_0
		clk125_out_pcie_compiler_0 : OUT STD_LOGIC;
		clk250_out_pcie_compiler_0 : OUT STD_LOGIC;
		clk500_out_pcie_compiler_0 : OUT STD_LOGIC;
		gxb_powerdown_pcie_compiler_0 : IN STD_LOGIC;
		pcie_rstn_pcie_compiler_0 : IN STD_LOGIC;
		phystatus_ext_pcie_compiler_0 : IN STD_LOGIC;
		pipe_mode_pcie_compiler_0 : IN STD_LOGIC;
		pll_powerdown_pcie_compiler_0 : IN STD_LOGIC;
		powerdown_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		rate_ext_pcie_compiler_0 : OUT STD_LOGIC;
		reconfig_clk_pcie_compiler_0 : IN STD_LOGIC;
		reconfig_fromgxb_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
		reconfig_togxb_pcie_compiler_0 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		refclk_pcie_compiler_0 : IN STD_LOGIC;
		rx_in0_pcie_compiler_0 : IN STD_LOGIC;
		rx_in1_pcie_compiler_0 : IN STD_LOGIC;
		rx_in2_pcie_compiler_0 : IN STD_LOGIC;
		rx_in3_pcie_compiler_0 : IN STD_LOGIC;
		rxdata0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdata1_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdata2_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdata3_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rxdatak0_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxdatak1_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxdatak2_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxdatak3_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxelecidle0_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxelecidle1_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxelecidle2_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxelecidle3_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxpolarity0_ext_pcie_compiler_0 : OUT STD_LOGIC;
		rxpolarity1_ext_pcie_compiler_0 : OUT STD_LOGIC;
		rxpolarity2_ext_pcie_compiler_0 : OUT STD_LOGIC;
		rxpolarity3_ext_pcie_compiler_0 : OUT STD_LOGIC;
		rxstatus0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxstatus1_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxstatus2_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxstatus3_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rxvalid0_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxvalid1_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxvalid2_ext_pcie_compiler_0 : IN STD_LOGIC;
		rxvalid3_ext_pcie_compiler_0 : IN STD_LOGIC;
		test_in_pcie_compiler_0 : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
		test_out_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
		tx_out0_pcie_compiler_0 : OUT STD_LOGIC;
		tx_out1_pcie_compiler_0 : OUT STD_LOGIC;
		tx_out2_pcie_compiler_0 : OUT STD_LOGIC;
		tx_out3_pcie_compiler_0 : OUT STD_LOGIC;
		txcompl0_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txcompl1_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txcompl2_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txcompl3_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txdata0_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdata1_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdata2_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdata3_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		txdatak0_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txdatak1_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txdatak2_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txdatak3_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txdetectrx_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txelecidle0_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txelecidle1_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txelecidle2_ext_pcie_compiler_0 : OUT STD_LOGIC;
		txelecidle3_ext_pcie_compiler_0 : OUT STD_LOGIC
	); 
END COMPONENT; 



COMPONENT alt_reconfig IS
	PORT
	(
		reconfig_clk		: IN STD_LOGIC ;
		reconfig_fromgxb	: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
		busy				: OUT STD_LOGIC ;
		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END COMPONENT;

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begin


safe_mode <= '1';
any_rstn <= pcie_rstn and local_rstn;
any_rst <= not any_rstn;	-- to drive gxb_powerdown and pll_powerdown

test_in(39 downto 16) <= (others => '0');

-- selects the layer to output onto the test_out bus
test_in(15 downto 13) <= "000";		-- selects the Lane
test_in(12) <= '0';					-- selects VC
test_in(11 downto 8) <= "0010";		-- 0000 = Transaction Layer, 0010 = PHY-MAC outputs

-- test_in[8 : 5] <= safe_mode ? 4'b0100 : usr_sw[3 : 0];	// PC 18May2010
--test_in(7 downto 5) <= "101";
test_in(7) <= '0';	-- Disable low power state negotiation
test_in(6 downto 5) <= "00";	-- b5 = completely disables compliance mode; never enter compliance mode
								-- b6 = forces compliance mode.
--test_in(4 downto 0) <= "01000";
test_in(4) <= '0';	-- Remote Boot mode
test_in(3) <= '1';	-- FPGA mode. Set to '1' for an FPGA implementation in order to appear compliant to other PCI Express components.
test_in(2) <= '0';	-- Descramble mode
test_in(1) <= '0';	-- Loopback Master
test_in(0) <= '0';	-- Simulation mode

-- LED logic
		alive_cnt <= (others => '0');
		alive_led <= '0';
		comp_led <= '0';
		L0_led <= '0';
		lane_active_led <= "0000";

--process (clk125_out_pcie_compiler_0, any_rstn)
--begin
--	if any_rstn = '0' then
--		alive_cnt <= (others => '0');
--		alive_led <= '0';
--		comp_led <= '0';
--		L0_led <= '0';
--		lane_active_led <= "0000";
--	elsif Rising_edge(clk125_out_pcie_compiler_0) then
--          alive_cnt <= alive_cnt + "1";
--          alive_led <= alive_cnt(24);
--          comp_led <= '0';
--          L0_led <= '0';
----          comp_led <= test_out[324 : 320] == 5'b00011;
----          L0_led <= test_out[324 : 320] == 5'b01111;
--          lane_active_led <= test_out(28 downto 25);
--	end if;
--end process;

-- DEBUG: bring out clock signals instead of its proper function
--lane_active_led(0) <= local_clk;
--lane_active_led(1) <= '0';
--lane_active_led(2) <= clk125_out_pcie_compiler_0;
--lane_active_led(3) <= ref_clk;

-- The PCI Express Compiler User Guide says you MUST instantiate an ALT_RECONFIG module to connect to :
-- reconfig_clk_pcie_compiler_0, reconfig_fromgxb_pcie_compiler_0, reconfig_togxb_pcie_compiler_0
-- PC 18May2010
alt_reconfig_instance : alt_reconfig
	port map(
		reconfig_clk		=> reconfig_clk_sig,
		reconfig_fromgxb	=> reconfig_fromgxb_sig,
		reconfig_togxb		=> reconfig_togxb_sig
	);

---- Altera's example used the RefClk/2 = 50MHz. DON'T USE THIS!!!! Says Altera
--process (ref_clk)
--begin
--	if Rising_edge(ref_clk) then
--          RefClk_Div2 <= not RefClk_Div2;
--	end if;
--end process;

-- Not equal Mark/Space ratio!
process (local_clk, any_rstn)
begin
--	if any_rstn = '0' then
--		Count <= 15;
--		Div3 <= '0';
--	elsif Rising_edge(local_clk) then
	if Rising_edge(local_clk) then
		if Count >= 2 then
			Count <= 0;
		else
			Count <= Count + 1;
		end if;

		if Count = 1 then
			Div3 <= '1';
		else
			Div3 <= '0';
		end if;
	end if;
end process;

--reconfig_clk_sig <= RefClk_Div2;	-- 37.5MHz to 50MHz. 100MHz/2 = 50MHz.
reconfig_clk_sig <= Div3;	-- 37.5MHz to 50MHz. 125MHz/2 = 41.67MHz.

---------------------------------------------------------------------------------
-- DEBUG. PC 20May2010
---------------------------------------------------------------------------------
--LCD_DATA(7 downto 0) <= local_rstn & pcie_rstn & reconfig_fromgxb_sig(0) & test_out(4 downto 0);	-- D0(7:0) 
--LCD_D_Cn <= clk125_out_pcie_compiler_0;		-- D1(0)
--LCD_CSn <= reconfig_clk_sig;				-- D1(2)
--LCD_WEn <= ref_clk;							-- D1(1)
LCD_DATA(7 downto 0) <= (others => '0'); 
LCD_D_Cn <= '0';
LCD_CSn <= '0';
LCD_WEn <= '0';
---------------------------------------------------------------------------------

  DUT : sopc_sgdma
    port map(
--      clk => local_clk,	-- PC 20May2010
      clk => clk125_out_pcie_compiler_0,
      
      clk125_out_pcie_compiler_0 => clk125_out_pcie_compiler_0,
      pcie_rstn_pcie_compiler_0 => pcie_rstn,
--      phystatus_ext_pcie_compiler_0 => '1',
--      pipe_mode_pcie_compiler_0 => '0',	-- 0 = use 1-bit serial interface, 1 = use PIPE for simulation
      phystatus_ext_pcie_compiler_0 => phystatus_ext_pcie_compiler_0_sig,
      pipe_mode_pcie_compiler_0 => pipe_mode_pcie_compiler_0_sig,	-- 0 = use 1-bit serial interface, 1 = use PIPE for simulation

-- PC 18May 2010
      reconfig_clk_pcie_compiler_0 => reconfig_clk_sig,
      reconfig_fromgxb_pcie_compiler_0 => reconfig_fromgxb_sig,
      reconfig_togxb_pcie_compiler_0 => reconfig_togxb_sig,

      refclk_pcie_compiler_0 => ref_clk,
--      reset_n => local_rstn,
      reset_n => any_rstn,
      rx_in0_pcie_compiler_0 => rx_in0,
      rx_in1_pcie_compiler_0 => rx_in1,
      rx_in2_pcie_compiler_0 => rx_in2,
      rx_in3_pcie_compiler_0 => rx_in3,
      rxdata0_ext_pcie_compiler_0 => rxdata0_ext_pcie_compiler_0_sig,
      rxdata1_ext_pcie_compiler_0 => rxdata1_ext_pcie_compiler_0_sig,
      rxdata2_ext_pcie_compiler_0 => rxdata2_ext_pcie_compiler_0_sig,
      rxdata3_ext_pcie_compiler_0 => rxdata3_ext_pcie_compiler_0_sig,
      rxdatak0_ext_pcie_compiler_0 => rxdatak0_ext_pcie_compiler_0_sig,
      rxdatak1_ext_pcie_compiler_0 => rxdatak1_ext_pcie_compiler_0_sig,
      rxdatak2_ext_pcie_compiler_0 => rxdatak2_ext_pcie_compiler_0_sig,
      rxdatak3_ext_pcie_compiler_0 => rxdatak3_ext_pcie_compiler_0_sig,
      rxelecidle0_ext_pcie_compiler_0 => rxelecidle0_ext_pcie_compiler_0_sig,
      rxelecidle1_ext_pcie_compiler_0 => rxelecidle1_ext_pcie_compiler_0_sig,
      rxelecidle2_ext_pcie_compiler_0 => rxelecidle2_ext_pcie_compiler_0_sig,
      rxelecidle3_ext_pcie_compiler_0 => rxelecidle3_ext_pcie_compiler_0_sig,
      rxstatus0_ext_pcie_compiler_0 => rxstatus0_ext_pcie_compiler_0_sig,
      rxstatus1_ext_pcie_compiler_0 => rxstatus1_ext_pcie_compiler_0_sig,
      rxstatus2_ext_pcie_compiler_0 => rxstatus2_ext_pcie_compiler_0_sig,
      rxstatus3_ext_pcie_compiler_0 => rxstatus3_ext_pcie_compiler_0_sig,
      rxvalid0_ext_pcie_compiler_0 => rxvalid0_ext_pcie_compiler_0_sig,
      rxvalid1_ext_pcie_compiler_0 => rxvalid1_ext_pcie_compiler_0_sig,
      rxvalid2_ext_pcie_compiler_0 => rxvalid2_ext_pcie_compiler_0_sig,
      rxvalid3_ext_pcie_compiler_0 => rxvalid3_ext_pcie_compiler_0_sig,

      test_in_pcie_compiler_0 => test_in,	-- Won't work if this is no connect!
--      test_out_pcie_compiler_0 => test_out,                                              

      tx_out0_pcie_compiler_0 => tx_out0,
      tx_out1_pcie_compiler_0 => tx_out1,
      tx_out2_pcie_compiler_0 => tx_out2,
      tx_out3_pcie_compiler_0 => tx_out3,

      gxb_powerdown_pcie_compiler_0 => gxb_powerdown_pcie_compiler_0_sig,
      pll_powerdown_pcie_compiler_0 =>  pll_powerdown_pcie_compiler_0_sig
      
    );

end rtl;
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