Anyone ported AN532 PCIe to Arria2GX dev kit?

Frederik,

All inputs at the top level can be left unconnected. In VHDL, just declare a signal called gxb_powerdown_pcie_compiler_0_sig and connect that to the vhdl instantiation. DO the same for the other inputs.

You can use the 125Mhz clock output from the PCIe IP as your application input clock instead of the local_clock.

The MOST IMPORTANT signals is actually the test_in, see below:

test_in(39 downto 16) <= (others => '0');

-- selects the layer to output onto the test_out bus

test_in(15 downto 13) <= "000"; -- selects the Lane

test_in(12) <= '0'; -- selects VC

test_in(11 downto 8) <= "0010"; -- 0000 = Transaction Layer, 0010 = PHY-MAC outputs

test_in(7) <= '0'; -- Disable low power state negotiation

test_in(6 downto 5) <= "00"; -- b5 = completely disables compliance mode; never enter compliance mode

-- b6 = forces compliance mode.

test_in(4) <= '0'; -- Remote Boot mode

test_in(3) <= '1'; -- FPGA mode. Set to '1' for an FPGA implementation in order to appear compliant to other PCI Express components.

test_in(2) <= '0'; -- Descramble mode

test_in(1) <= '0'; -- Loopback Master

test_in(0) <= '0'; -- Simulation mode

Regards,

Peter