Honored ContributorHi,
I have 100 MHz clock source directly connected to FPGA (Aria V device), using this I want to generate 250 MHZ clock from FPGA. Is ALTPLL IP suitable for this requirement? Pls suggest. And also max how many different clock outputs i can generate using this IP. Thanks, Ashwini
Honored ContributorYes, you'll be able to do that in Arria V with the PLL. You can have up to 18 output clocks from the PLL in Arria V. Play around with the IP configuration tool to determine which combinations of output clocks are valid.
Refer to the altera phase-locked loop (altera pll) ip core user guide (https://www.altera.com/en_us/pdfs/literature/ug/altera_pll.pdf) for full details. Cheers, AlexHonored ContributorThe Arria V PLL output frequency can go up to 500MHz in the slowest speed grade for external clock output. So the 250MHz should not be an issue.
Honored ContributorJust to add that the PLL output frequency to the core logic might be lower than the external clock output. You may double check on the datasheet.
Honored ContributorThanks for all the replies.
-- Ashwini
