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Altera_Forum
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10 years ago

ALTPLL multiplication factor

Hi, I have 100 MHz clock source directly connected to FPGA (Aria V device), using this I want to generate 250 MHZ clock from FPGA. Is ALTPLL IP suitable for this requirement? Pls suggest. And a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, you'll be able to do that in Arria V with the PLL. You can have up to 18 output clocks from the PLL in Arria V. Play around with the IP configuration tool to determine which combinations of output clocks are valid.

Refer to the altera phase-locked loop (altera pll) ip core user guide (https://www.altera.com/en_us/pdfs/literature/ug/altera_pll.pdf) for full details.

Cheers,

Alex