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Honored ContributorALTLVDS input bit being shifted too soon.
Hi,
I am trying to setup ALTLVDS on a Stratix IV GX part. When simulating it I see that on every alternate cycles, the serial bit is shifted in too soon. Please see the attached image. I am not sure why this happens. Any thoughts? My design criteria - ALTLVDS in external pll and non-dpa mode. 350Mhz reference clock. 700Mbps datarate. 14 bit words over two channels therefore deserialization factor of 7. http://dl.dropbox.com/u/5702055/003%20sparekh.gif TIA. Sanjay4 Replies
Altera_ForumHi FvM,
Thank you helping. Yes! This and a few other errors created a mess that completely confounded me. Bottomline though is that all the PLL settings and clock relationships are based on the slow clock. In otherwords, it is assumed that the PLL reference input is of the same frequency as the slow clock (after deserialization). In my case, I was using the fast clock to feed the PLL reference input because that is what I had. This important part was not obvious to me. Thanks. Sanjay- Altera_Forum
I'm not able to understand the timing of all signals. rx_enable is e.g. said to have slow clock frequency in the MegaWizard.
- Altera_Forum
In the picture below - http://dl.dropbox.com/u/5702055/004%20sparekh.gif
fr = frame rx_out = 14bit deserialized output word. You can also look at the rx_out_a, rx_out_b which are shown in hex. They are deserialized outputs from serial channels rx_in[0] and rx_in[1] respectively. DCO is the input fast clock. PCLK is the output slow clock generated by the external pll. Please ignore the fact that the phase is not aligned with the output. I believe that is another issue. I have used the same equations as noted in the high-speed i/o section of StratixIVGX handbook. Thanks. - Altera_Forum
To understand a possible error, I would like to see the frameclock and the deserialized output data. Otherwise I'm unable to see the word boundary and determine if there is an error at all.
