ALTLVDS input bit being shifted too soon.

In the picture below - http://dl.dropbox.com/u/5702055/004%20sparekh.gif

fr = frame

rx_out = 14bit deserialized output word. You can also look at the rx_out_a, rx_out_b which are shown in hex. They are deserialized outputs from serial channels rx_in[0] and rx_in[1] respectively. DCO is the input fast clock.

PCLK is the output slow clock generated by the external pll. Please ignore the fact that the phase is not aligned with the output. I believe that is another issue. I have used the same equations as noted in the high-speed i/o section of StratixIVGX handbook.

Thanks.