ALTLVDS input bit being shifted too soon.

Hi FvM,

Thank you helping. Yes! This and a few other errors created a mess that completely confounded me. Bottomline though is that all the PLL settings and clock relationships are based on the slow clock. In otherwords, it is assumed that the PLL reference input is of the same frequency as the slow clock (after deserialization). In my case, I was using the fast clock to feed the PLL reference input because that is what I had.

This important part was not obvious to me.

Thanks.

Sanjay