Altera_Forum
Honored Contributor
Honored ContributorAltera Modelsim problems
Hi All,
I am a newcomer to VHDL having done a previous course using Verilog. I have a clock divider which produces one clock T-state-wide pulses from a 50Mhz system clock (say, every 10 milliseconds, every 50 milliseconds, etc). This is instantiated in a switch debounce entity that provides a little more than just a debounced switch pulse. This has compiled fine and produced sensible simulation results using Altera's simulation tool on Quartus v9.1. Then I created a simple test bench. I have used the native-link simulator stuff in Quartus by going to Assignments->EDA Tool Settings and filling in the Simulation card appropriately with the Altera Modelsim as the tool. The test bench entity is the top level and instantiates the switch debouncer entity as a DUT. Then I go to Processing->Start->Start Analysis and Elaboration. This works fine. Then Processing->Start->Start EDA Netlist Writer. Fine. Then Tools->Run EDA Simulation Tool->EDA Gate Level Simulation. All is well, it pulls in all the Cyclone II information from the project set up, brings up a waveform display in Modelsim, and puts signals and waves into it. And the outputs respond to the input stimulus with clock-to-output delays taken from the Altera data. So timing simulation is fine. But initially, especially if it was a more complicated design, I might want to just check out the functionality first by using Tools->Run EDA Simulation Tool->EDA RTL Simulation. This runs but here is the problem, or one of the problems. The waveforms are produced but there are no output responses to input stimulus. The clock is fine and the inputs follow their patterns in the test bench, but the outputs do nothing. So timing simulation works but RTL simulation doesn't. Why is this? Incidentally, Quartus shows an RTL schematic in Tools->Netlist Viewers->RTL Viewer which looks fine and in order. (I've had Verilog designs that weren't working that have produced RTL diagrams like plates of spaghetti, and rightly so!). The other problem is a string of warnings like this: # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut and so on up to the set run time of 15us. All the signals/inputs/outputs in the entities are standard_logic except for the counters which are standard_logic_vectors like this: SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0); n is declared earlier in the GENERIC section as a NATURAL := specified value. The specified value will be different depending on whether I've commented in or out a small value for testing or large value for real use. I understand that there are one or two ways of turning these warning messages off although the methods I've tried have not succeeded. On the other hand I would rather be warned if something isn't quite right and take steps to kill the problem at source. Can anyone throw any light on this? Thanks.
