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Altera_Forum
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15 years ago

Altera Modelsim problems

Hi All, I am a newcomer to VHDL having done a previous course using Verilog. I have a clock divider which produces one clock T-state-wide pulses from a 50Mhz system clock (say, every 10 milli...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := B"00";

SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := B"0000";

Not elegant and there must be a better way of doing it

--- Quote End --- 

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := (others => '0');
SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := (others => '0');

--- Quote Start ---

variable TenmsCntr : natural range 0 to 2**(n - 1) := 0;

--- Quote End ---

warning : It means 0 to 128 if n=8. That is surely not what you want.

You are making an error, you should write 
variable TenmsCntr : natural range 0 to (2**n) - 1 := 0; -- means 0 to 255 if n=8

NB : You write too much. "Keep It Simple and St*pid"

Happy to help you.