Altera Modelsim problems

Many thanks mmTsuchi.

Sorry about large text block - just setting the scene.

The resolution was set at 100ps. But from what you said I went and looked at my two counters (in the switch debounce module) and set their initial states as zero like this:

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := B"00";

SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := B"0000";

Not elegant and there must be a better way of doing it. But, re-did the Processing->Start->Start Analysis and Elaboration, followed by a new EDA Netlist and then ran the RTL Simulation tool as before. And this time there were no warnings at all and all output signals were present and correct. Bang in sync with the clock of course because there is no timing information about the Cyclone chip (the one in my DE2 development board) but the RTL simulation worked. The 'n' values above are small because they are just for running simulations like this. They are 'naturals'.

What would you say is the most elegant way of defining counters that can be used for timing or cycling operations like these and with count range definable using different generics to produce small counters for desktop simulation and large counters for real world use? Actually in my clock divider I used variables like this for my counter declarations:

variable TenmsCntr : natural range 0 to 2**(n - 1) := 0;

so perhaps that is what I should do for the debouncer.

I never use counter outputs as clock signals of course. I always use the system clock for that. The clock divider for this design produces 20ns wide (1/50MHz) enable signals at 10ms intervals, 50ms intervals, 0.5 second intervals (for a clock colon) and 1 second intervals (for a microwave oven cook time down counter).

Thanks again.