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Altera_Forum
Honored Contributor
Honored ContributorAltera Modelsim problems
Hi All, I am a newcomer to VHDL having done a previous course using Verilog. I have a clock divider which produces one clock T-state-wide pulses from a 50Mhz system clock (say, every 10 milli...
Altera_ForumHonored Contributor
Honored ContributorHi,
Large block of text :-) --- Quote Start --- So timing simulation works but RTL simulation doesn't --- Quote End --- Verify time resolution. RTL simulation are usually in ps maybe other forumers have ideas. --- Quote Start --- # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut --- Quote End --- It usually means that there are conflicts or undefined signals. And those signal are on one operand of your +,-,*,/ operations You try to make s <= a+b; with A = "uuuuuu1" for example. Nota Bene : std_logic are resolved type.
