Altera Modelsim problems

Hi,

Large block of text :-)

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So timing simulation works but RTL simulation doesn't

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Verify time resolution. RTL simulation are usually in ps

maybe other forumers have ideas.

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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut

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It usually means that there are conflicts or undefined signals. And those signal are on one operand of your +,-,*,/ operations

You try to make s <= a+b; with A = "uuuuuu1" for example.

Nota Bene : std_logic are resolved type.