Altera FPGA with TI A/D EVM

Hi,

Thanks for your reply. I am glad to know that they can work together.

I am developing a test measurement unit with 8 channel A/D card, FPGA and DSP unit. The idea is to transfer the 8 channel data continuously from FPGA to DSP for further processing. This FPGA has enough computation power to do the job, right ?

Where should I look for FPGA code to transfer the data to FPGA ?

Thanks.

I'm sure, very sure, there will be enough grunt in the DE2-115's FPGA.

As for the code - isn't that for you to write? Refer to the datasheet for the ADC. There are some very clear diagrams showing the relevant data stream signal timings.

Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed, in the same way the datasheet refers to a 12x clock from which the data streams are generated. You may be restricted by the signals that are carried across the interconnect board. However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there.

Regards,

Alex

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Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed,

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This statement is confusing: DDR means you have to capture (or emit) data at both the negative and positive edge of the clock. But this only happens at the 'periphery' of the FPGA.

This 'job' is handled by the ALTDDIO_xxx primitives/functions provided by Altera. Inside the FPGA data is consumed (produced) at double the width of the physical bus but at the base clock speed.

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However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there.

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This particular ADC, the ADS5281 (I believe most of TI ADCs), has it LCLK shifted by 90 degrees so you can do without a PLL.

Hi,

There is always some sample code provided by the vendor which could be modified to suit your application. I was asking for that code.

josyb is right. Using Altera's ALTDDIO_IN primitive is a much cleaner way to implement this interface.

As for vendors 'always' providing sample code - I don't agree. Devices are often intended to interface to all manner of 3rd party devices. Vendors aren't likely to offer code for all of them.

There may well be some sample code available from TI but it's not obviously available on their site. If this forum is not forthcoming then I suggest you ask TI.

I have no idea how VHDL/Verilog code works or can be implemented but I will try my best to proceed.

Thanks. I appreciate your help.

Hi,

I have one confusion, how the LVDS output data is being de-serialized here ?

You need to use Altera's ALTDDIO_IN primitive. You will feed it with two signals from the ADS5282: LCLK and a data stream e.g. OUT1.

Internally to the FPGA, ALTDDIO_IN will present two bits, one generated from LCLK's rising edge and the other from the falling edge.

Considering 6 LCLK clock cycles (12 consecutive edges) will reveal the 12-bit resulting conversion.

It looks like you also need to use ADCLK for framing - i.e. telling you where one ADC sample result ends and the next starts.

Regards,

Alex

Thanks Alex.

Data coming from A/D converter in my case for one channel is 12 bits x 50 MHz = 600 Mbps. I couldn't found the data rate for LVDS receiver in the data sheet. Can DE2-115 handle it ?

Do you know where can I find that information ?

Thanks.