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Altera_Forum
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12 years ago

Altera FPGA with TI A/D EVM

Hi, I am totally new to this FPGA world so please ignore my question if they seem basic or stupid. I want to interface 8 channel, 12 bits resolution ADC with at least 50 MSPS A/D FPGA. I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks Alex.

Data coming from A/D converter in my case for one channel is 12 bits x 50 MHz = 600 Mbps. I couldn't found the data rate for LVDS receiver in the data sheet. Can DE2-115 handle it ?

Do you know where can I find that information ?

Thanks.