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Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed,
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This statement is confusing: DDR means you have to capture (or emit) data at both the negative and positive edge of the clock. But this only happens at the 'periphery' of the FPGA.
This 'job' is handled by the ALTDDIO_xxx primitives/functions provided by Altera. Inside the FPGA data is consumed (produced) at double the width of the physical bus but at the base clock speed.
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However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there.
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This particular ADC, the ADS5281 (I believe most of TI ADCs), has it LCLK shifted by 90 degrees so you can do without a PLL.
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