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Altera_Forum
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12 years ago

Altera FPGA with TI A/D EVM

Hi, I am totally new to this FPGA world so please ignore my question if they seem basic or stupid. I want to interface 8 channel, 12 bits resolution ADC with at least 50 MSPS A/D FPGA. I ...
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Altera_Forum
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12 years ago

You need to use Altera's ALTDDIO_IN primitive. You will feed it with two signals from the ADS5282: LCLK and a data stream e.g. OUT1.

Internally to the FPGA, ALTDDIO_IN will present two bits, one generated from LCLK's rising edge and the other from the falling edge.

Considering 6 LCLK clock cycles (12 consecutive edges) will reveal the 12-bit resulting conversion.

It looks like you also need to use ADCLK for framing - i.e. telling you where one ADC sample result ends and the next starts.

Regards,

Alex