Honored Contributor
Honored ContributorI'm sure, very sure, there will be enough grunt in the DE2-115's FPGA.
As for the code - isn't that for you to write? Refer to the datasheet for the ADC. There are some very clear diagrams showing the relevant data stream signal timings. Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed, in the same way the datasheet refers to a 12x clock from which the data streams are generated. You may be restricted by the signals that are carried across the interconnect board. However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there. Regards, Alex
