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Altera_Forum's avatar
Altera_Forum
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11 years ago

Altera DDR3 Memory Controller and PHY

I am using Altera DDR3 Memory Controller + Uniphy in Stratix V. I have a board with four (4) DDR3 SODIMMs which have been designed to work up to 800 MHz. I have four DDR3 Controller + Uniphy, one for each SODIMM.

I would like to know if I can use the same Controller + PHY for testing my SODIMM interfaces at clock frequencies ranging from 200 to 800 MHz, or would I need to generate different FPGA images having different Controller + PHY generated at different frequencies?

Thank you!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    How do you expect to generate the range of clock frequencies without regenerating the FPGA images? Are you expecting to simply clock the Stratix device with different frequencies?

    The DDR clock sourced from the FPGA will come from a PLL that has been specifically configured to accept a particular input clock frequency and generate the 800MHz clock you mention. So, if you wish to change that frequency you'll need to change the PLL settings and regenerate the FPGA image. Simply reducing the frequency of the clock into the PLL by (for example) a factor of 4, without changing the PLL settings and regenerating, might well work but isn't recommended.

    Regards,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks Alex!

    I guess the DLLs could also cause problems if the frequency changes too much from what it was generated with?

    Regards

    Arnab
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Alex,

    A follow up question - can we not have a configurable external PLL to source the DDR clock, instead of using the PLL inside the DDR PHY?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I wouldn't want to sign of a design with the PLLs being driven by a clock frequency other than the one it was designed for - although it may well work...

    You could use an external PLL to source the clock to the FPGA, but the UniPhy would still want to instantiate a PLL for the DDR memory interface. I don't think you'll gain anything, except a design that's trickier to constrain.

    If you want to try different frequencies, I suggest you regenerate your design.

    Regards,

    Alex