Forum Discussion

Honored Contributor

11 years ago

Altera DDR3 Memory Controller and PHY

I am using Altera DDR3 Memory Controller + Uniphy in Stratix V. I have a board with four (4) DDR3 SODIMMs which have been designed to work up to 800 MHz. I have four DDR3 Controller + Uniphy, one for...

Altera_Forum

Honored Contributor

11 years ago

Alex,

A follow up question - can we not have a configurable external PLL to source the DDR clock, instead of using the PLL inside the DDR PHY?

Forum Discussion

Altera DDR3 Memory Controller and PHY

Recent Discussions

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

IBIS models GTS banks agilex 5E