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Altera_Forum
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12 years ago

Altera DDR3 Memory Controller and PHY

I am using Altera DDR3 Memory Controller + Uniphy in Stratix V. I have a board with four (4) DDR3 SODIMMs which have been designed to work up to 800 MHz. I have four DDR3 Controller + Uniphy, one for...
Altera_Forum's avatar
Altera_Forum
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12 years ago

How do you expect to generate the range of clock frequencies without regenerating the FPGA images? Are you expecting to simply clock the Stratix device with different frequencies?

The DDR clock sourced from the FPGA will come from a PLL that has been specifically configured to accept a particular input clock frequency and generate the 800MHz clock you mention. So, if you wish to change that frequency you'll need to change the PLL settings and regenerate the FPGA image. Simply reducing the frequency of the clock into the PLL by (for example) a factor of 4, without changing the PLL settings and regenerating, might well work but isn't recommended.

Regards,

Alex