Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Altera DDR3 Memory Controller and PHY

I am using Altera DDR3 Memory Controller + Uniphy in Stratix V. I have a board with four (4) DDR3 SODIMMs which have been designed to work up to 800 MHz. I have four DDR3 Controller + Uniphy, one for...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I wouldn't want to sign of a design with the PLLs being driven by a clock frequency other than the one it was designed for - although it may well work...

You could use an external PLL to source the clock to the FPGA, but the UniPhy would still want to instantiate a PLL for the DDR memory interface. I don't think you'll gain anything, except a design that's trickier to constrain.

If you want to try different frequencies, I suggest you regenerate your design.

Regards,

Alex