Altera CycloneIII FPGA PLL problem

The PLL input clock is 27M. It is multipied and output a clock of 270M to supply the ASI IP core. 8 PCB boards are in test and downloaded the same FPGA program. The problem is, 4 out of 8 boards can access the process with a correct PLL output 270M clock, while 4 fo them cannot. In the faulty ones, it shows "waiting for clock" or a quite mess wave when you use the faulty output clock as the signaltap sampling clock. If you draw the faulty output clock to a pin, the wave amplitude is much smaller than the right ones. Can I define the problem is on PLL?