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Altera_Forum
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15 years ago

Altera CycloneIII FPGA PLL problem

The PLL input clock is 27M. It is multipied and output a clock of 270M to supply the ASI IP core. 8 PCB boards are in test and downloaded the same FPGA program. The problem is, 4 out of 8 boards can ...
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Altera_Forum
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15 years ago

Thank you for your reply,dear std_logic_vector!

I have routed the input clock to an output pin and checked it.27M,the output clock is all right.So I think the problem isnot bad joints.

The locked signal in faulty PCB is low,but the locked signal in PCB that can works well is also low.It is very strange.